1. Field of the Invention
The present invention relates to a silicon wafer, and to a method of manufacturing the same, which can suppress occurrence of slip dislocations and warpage in semiconductor wafer manufacturing, in particular, in device manufacturing processes.
2. Background Art
Silicon wafers used as a substrate for semiconductor devices or the like are manufactured by slicing a silicon single-crystal ingot and performing heat treatment, mirror polishing, and other conventional processing steps. As a method of manufacturing a silicon single-crystal ingot, for example, the Czochralski method (CZ method) is generally used. The CZ method occupies a large part of manufacturing of silicon single-crystal ingots because a large-diameter single-crystal ingot can be easily obtained, and defects can be controlled relatively easily.
In a silicon single crystal pulled by the CZ method (referred to as “CZ—Si”), crystal defects called grown-in defects are present. The CZ—Si includes oxygen between lattices in an oversaturated state. However, the oversaturated oxygen causes a microscopic defect called a Bulk Micro Defect (“BMD”) by a heat treatment (annealing) performed later.
In order to form a semiconductor device from a silicon wafer, crystal defects are required to be absent in the semiconductor device forming region. When a crystal defect is present on a surface for forming a circuit, the defective portion causes circuit breakdown or other defects. On the other hand, an appropriate number of BMDs are required to be present in the silicon wafer. This is because the BMDs function to getter metal impurities which cause semiconductor devices to malfunction.
In order to satisfy the above requirements, high-temperature annealing of the silicon wafer to induce BMD formation in the silicon wafer to form an Intrinsic Gettering layer (“IG layer”) can also eliminate grown-in defects present on the surface of the silicon wafer to form a Denuded Zone (“DZ layer”) layer having an extremely small number of crystal defects.
As a concrete example, JP published application 10-98047 discloses a method which performs high-temperature annealing of a nitrogen-containing substrate to reduce grown-in defects on the surface and forms BMDs having nitrogen as nuclei in the substrate.
However, the DZ layer formed on the upper and lower surfaces of the silicon wafer by the high-temperature annealing process has an oxygen concentration which is extremely low because of outward diffusion of oxygen during heat treatment. As a result, the ability to reduce propagation of dislocation defects on the upper and lower surfaces of the wafer is extremely low. For this reason, due to micro-scratches on the upper and lower surfaces caused in the annealing step, dislocation defects (“slip”) easily propagate in the bulk. Propagation of slip dislocations undesirably decreases the strength of the silicon wafer. For example, when a wafer is annealed while being supported by a heat treatment susceptor or the like, slip dislocations frequently extend from a supported portion at the periphery of the wafer to the lower surface of the wafer. The slip dislocation may extend from a silicon wafer edge, for example.
When the strength of the silicon wafer is deteriorated, the wafer may be damaged during the manufacturing steps, or the wafer may be broken. However, the DZ layer is indispensable to manufacturing of a semiconductor device. A silicon wafer having, at the same time, a DZ layer and excellent strength characteristics is desired.
In the conventional technique described in JP 10-98047 deterioration of the strength of a silicon wafer is not considered. A silicon wafer formed by the above method cannot avoid slip dislocation propagation.
On the other hand, in order to prevent occurrence of slip dislocations, a method which generate BMDs at a high concentration has also been proposed. More specifically, a silicon wafer manufacturing method has been proposed in which a rapid heating/cooling rate heat treatment is performed on a wafer in a mixed atmosphere of nitrogen and inert gas, or ammonia and inert gas, at a temperature of 500° C. to 1200° C. for 1 minute to 600 minutes to form oxygen precipitation nuclei having a size of 20 nm or less in a BMD layer at a concentration of 1×1010/cm3 or more (JP published application 2006-40980). JP published application 2006-269896 discloses a silicon wafer manufacturing method in which heat treatment is performed on a silicon wafer having an oxygen concentration of 1.2×1018 atoms/cm3 to 1.4×1018 atoms/cm3 and a carbon concentration of 0.5×1016 atoms/cm3 to 2×1017 atoms/cm3 in a non-oxidizing atmosphere under the conditions: a temperature of 1100° C. to 1250° C.; for 1 hour to 5 hours; and a temperature ramp of 0.1 to 1° C./minute over a temperature range of 1100° C. to 1250° C., to form BMDs each having a size of 150 nm or less at a concentration of 5×109/cm3 or more. A silicon wafer in which a heat treatment is repeated several times to generate BMDs at a high concentration (1×1010/cm3 to 1×1012/cm3) is proposed in JP published application 08-213403. Furthermore, a silicon wafer in which BMDs each of which is located at a position having a depth of 50 μm from a surface and has a size of 10 nm or more to 50 nm or less are formed at a concentration of 5×1011/cm3 to suppress slip and warpage is proposed in JP published application 2008-160069.
However, in recent years, as the silicon wafers have increased in diameter, and as the integration density of semi-conductor device patterns has increased, warpage of the wafer becomes problematic in addition to occurrence of slip dislocation.
As heat treatment furnaces, a batch type heat treatment furnace and an RTA are known. Slip propagates from a contact between the lower surface of a silicon wafer edge and a silicon wafer holding portion or a silicon wafer edge portion. The propagating slip extends in the [110] direction, and, depending on circumstances, the silicon wafer may be damaged or broken. Warpage is a phenomenon in which a silicon wafer is deformed by thermal distortion in a heat treatment. Warpage of a silicon wafer before heat treatment to give desired characteristics is suppressed to 10 μm or less. However, when heat treatment is performed, the difference between a peak and a trough of the warped wafer reaches several tens of micrometers. A semiconductor device pattern cannot correctly be exposed (photolithography) on such a warped wafer surface and thus causes a decrease in yield of semiconductor devices.
The problem of warpage is particularly conspicuous when a wafer diameter is 200 mm or more. In particular, problems caused by warpage in a batch type heat treatment cannot be solved without giving attention to BMD concentration and size in the surface layer. As described above, even when BMDs are controlled so as to be formed at a position having a depth of 50 μm or more and to have small sizes, the problem cannot be avoided.